prompt stringlengths 450 62.1k | response stringlengths 1.28k 36.6k | top_module stringlengths 1 104 | instance stringlengths 2 109 |
|---|---|---|---|
Read the SystemVerilog module `top` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// Assignment via `always_comb` to an unpacked array within an interface.
// Use `foreach` loop to iterate through array elements.
/* NOTE: Lines 7, 8, 28, 29, 23, and 24; ordered... |
<think>
* DUT: `top` module.
* Functionality: Broadcasts input `i_a` (1 bit) to output `o_a` (unpacked array of 8 bits).
* Interface: `I` interface used inside `top` to handle the logic.
* Test Plan:
* DUT instance name: `tb_top`.
* Reference model: `exp_o_a[i] = i_a`.
*... | top | tb_top |
Read the SystemVerilog module `finalproj_soc_mm_interconnect_0_router_002` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// soft... |
<think>
* DUT: `finalproj_soc_mm_interconnect_0_router_002`
* Function: Merlin Router. Routes packets from sink to source.
* Routing Logic: Extracts Destination ID from `sink_data[93:90]`. Based on the code, `src_channel` is always `13'b1` because the `default_src_channel` is `13'b1` (from `DEFAULT_CHANN... | finalproj_soc_mm_interconnect_0_router_002 | tb_top |
Read the SystemVerilog module `bsp_top_altera_merlin_multiplexer_1921_6gqhlja` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// (C) 2001-2021 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// ... |
<think>
* DUT: `bsp_top_altera_merlin_multiplexer_1921_6gqhlja`.
* Function: 1-input Merlin Multiplexer.
* RTL Logic: Purely combinational passthrough.
* Interfaces: `sink0` (input) and `src` (output).
* Signals: `valid`, `data`, `channel`, `startofpacket`, `endofpacket`, `ready`.
* Con... | bsp_top_altera_merlin_multiplexer_1921_6gqhlja | tb_bsp_top_altera_merlin_multiplexer_1921_6gqhlja |
Read the SystemVerilog module `Multiplexer_2to1` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module Multiplexer_2to1
#(parameter WIDTH = 1)
(ctrl,
D0,
D1,
S);
input ctrl;
input [WIDTH-1:0] D0;
input [WIDTH-1:0] D1;
output [WIDTH... |
<think>
* DUT: `Multiplexer_2to1` (parameterized `WIDTH`).
* Functionality: `S = (ctrl == 0) ? D0 : D1`.
* Requirement: Expert SystemVerilog verification engineer.
* Test Plan Implementation:
* Reference Model: Simple behavioral logic.
* DUT Instance Name: `tb_Multiplexer_2to1` ... | Multiplexer_2to1 | tb_Multiplexer_2to1 |
Read the SystemVerilog module `prim_secded_22_16_dec` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDE... |
<think>
* DUT: `prim_secded_22_16_dec`.
* Input: `data_i [21:0]`.
* Outputs: `data_o [15:0]`, `syndrome_o [5:0]`, `err_o [1:0]`.
* Function: SECDED decoder.
* Constraints: Must be compatible with `iverilog -g2012`. No classes, no `covergroups`, no concurrent SVA. Use immediate assertions, tas... | prim_secded_22_16_dec | test_prim_secded_22_16_dec |
Read the SystemVerilog module `k0_ZTS6MMstv3_bb_ZTS6MMstv3_B12_stall_region` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// -------------------------------------------------------------------------
// High Level Design Compiler for Intel(R) FPGAs Version 20.... |
<think>
* Module Name: `k0_ZTS6MMstv3_bb_ZTS6MMstv3_B12_stall_region`
* Inputs: `in_stall_in` (1), `in_valid_in` (1), various `in_c0_exe...` signals (widths: 1, 32, 64), `clock`, `resetn`.
* Outputs: `out_stall_out` (1), `out_valid_out` (1), corresponding `out_c0_exe...` signals.
* Logic:
*... | k0_ZTS6MMstv3_bb_ZTS6MMstv3_B12_stall_region | uut |
Read the SystemVerilog module `Multiplexer_AC__parameterized` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
module Multiplexer_AC__parameterized #(parameter INIT_VALUE=8'hB8)
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:... |
<think>
* Top module: `Multiplexer_AC__parameterized`
* Parameters: `INIT_VALUE` (8'hB8) - *Wait, looking at the code, this parameter is defined but never used in the logic.*
* Inputs: `ctrl` (1 bit), `D0` (1 bit), `D1` (1 bit).
* Output: `S` (1 bit).
* Logic: `assign S = (ctrl) ? D1 : D0;`
... | Multiplexer_AC__parameterized | Multiplexer_AC__parameterized_tb |
Read the SystemVerilog module `accelerator_design` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
////////////////////////////////////////////////////////////////////////////////
// __ _ _ _ //
//... |
<think>
* DUT: `accelerator_design` (8-bit adder with 9-bit output, asynchronous active-high reset, synchronous output).
* Requirement: Complete self-checking SystemVerilog testbench.
* Test Plan:
* Reset: Power-on, Asynchronous, De-assertion.
* Directed: Zeroes, Identity, Max (overfl... | accelerator_design | test_accelerator_design |
Read the SystemVerilog module `prim_secded_22_16_enc` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Ap... |
<think>
* DUT: `prim_secded_22_16_enc` (16-bit input, 22-bit output).
* Functionality: Combinational SECDED encoder.
* Parity calculation: XOR reduction of input data with specific masks.
* Test Plan:
* Reference model implementing the same masks.
* Exhaustive testing ($2^{16}$ ... | prim_secded_22_16_enc | test_prim_secded_22_16_enc |
Read the SystemVerilog module `adder` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module adder #(parameter N = 32)(a, b, cin, s, cout);
input logic [N-1:0] a;
input logic [N-1:0] b;
output logic [N-1:0] s;
input logic cin;
output logic cout;
assign {cou... |
<think>
* DUT: `adder` with parameter `N` (default 32).
* Inputs: `a`, `b`, `cin`.
* Outputs: `s`, `cout`.
* Logic: `{cout, s} = a + b + cin`.
* Test Plan requirements:
* Reference model: `{expected_cout, expected_s} = a + b + cin`.
* Directed Boundary Cases: All Zeros, Ze... | adder | dut |
Read the SystemVerilog module `accelerator_design` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
////////////////////////////////////////////////////////////////////////////////
// __ _ _ _ //
//... |
<think>
* DUT: `accelerator_design` (registered 8-bit adder, 9-bit output, asynchronous active-high reset).
* Functional Intent: `out <= in1 + in2` on `posedge clk`.
* Reset: Asynchronous active-high, `out` becomes 0.
* Constraints for TB:
* Self-checking.
* Reference model: `ex... | accelerator_design | dut |
Read the SystemVerilog module `slavereg_comp_B1_start_merge` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
// -------------------------------------------------------------------------
// High Level Design Compiler for Intel(R) FPGAs Version 21.1 (... |
<think>
* Module Name: `slavereg_comp_B1_start_merge`
* Inputs: `in_stall_in`, `in_valid_in_0`, `in_valid_in_1`, `clock`, `resetn`.
* Outputs: `out_stall_out_0`, `out_stall_out_1`, `out_valid_out`.
* Logic:
* `valid_or_q = in_valid_in_0 | in_valid_in_1;`
* `stall_out_q = valid_o... | slavereg_comp_B1_start_merge | slavereg_comp_B1_start_merge_tb |
Read the SystemVerilog module `chext_mem_1w1r` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
module chext_mem_1w1r #(
parameter COUNT = 16,
parameter ADDR_WIDTH = 4,
parameter DATA_WIDTH = 16
) (
input clock,
// Port A
inpu... |
<think>
* Module: `chext_mem_1w1r` (1-Write, 1-Read memory).
* Parameters: `COUNT` (16), `ADDR_WIDTH` (4), `DATA_WIDTH` (16).
* Port A (Write): `addrA`, `writeEnA`, `dataInA`.
* Port B (Read): `addrB`, `dataOutB`.
* Logic: Synchronous write on `posedge clock` if `writeEnA` is high. Asynchrono... | chext_mem_1w1r | chext_mem_1w1r_verif_tb |
Read the SystemVerilog module `cluster_clock_inverter` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the ... |
<think>
* Design: `cluster_clock_inverter` (simple inverter: `clk_o = ~clk_i`).
* Goal: Complete, self-checking SystemVerilog testbench.
* Test Plan Requirements:
* Functional intent: `clk_o` must be the inverse of `clk_i`.
* Scenarios: Static Low, Static High, Toggling Clock, X-Propa... | cluster_clock_inverter | cluster_clock_inverter_verif_tb |
Read the SystemVerilog module `prim_secded_hamming_76_68_enc` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-L... |
<think>
* Module: `prim_secded_hamming_76_68_enc`.
* Functionality: SECDED (Single Error Correction, Double Error Detection) Hamming Encoder.
* Input: `data_i` [67:0] (68 bits).
* Output: `data_o` [75:0] (76 bits).
* Implementation: Combinational logic. It maps 68 bits of data to a 76-bit cod... | prim_secded_hamming_76_68_enc | prim_secded_hamming_76_68_enc_tb |
Read the SystemVerilog module `rsdec_chien_scale1` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module rsdec_chien_scale1 (y, x);
input [7:0] x;
output [7:0] y;
reg [7:0] y;
always @ (x)
begin
y[0] = x[7];
y[1] = x[0] ^ x[7];
y[2] = x[1] ^ x[7];
... |
<think>
* DUT: `rsdec_chien_scale1`
* Functionality: Combinational logic mapping 8-bit input `x` to 8-bit output `y`.
* Equations:
* `y[0] = x[7]`
* `y[1] = x[0] ^ x[7]`
* `y[2] = x[1] ^ x[7]`
* `y[3] = x[2]`
* `y[4] = x[3]`
* `y[5] = x[4]`
... | rsdec_chien_scale1 | rsdec_chien_scale1_verif_tb |
Read the SystemVerilog module `system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools... |
<think>
`system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux`
Demultiplexer (specifically a "Merlin Demultiplexer").
Takes a "sink" interface (valid, data, channel, sop, eop) and routes it to "source" interfaces based on the `sink_channel` signal.
* `NUM_OUTPUTS = 1`
* `ST_DATA_W = 8... | system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux | tb |
Read the SystemVerilog module `halves_sum` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
module halves_sum(
input [31:0] in,
output reg [15:0] out
);
always @(*) begin
out = (in[31:16] + in[15:0]);
end
endmodule
```
Cover... |
<think>
* Module: `halves_sum`
* Input: `in [31:0]`
* Output: `out [15:0]` (reg, but assigned in `always @(*)`, making it combinational)
* Function: `out = (in[31:16] + in[15:0])`
* Logic: 16-bit unsigned addition of the upper half and lower half of a 32-bit input. Since the output is 16-bit,... | halves_sum | halves_sum_verif_tb |
Read the SystemVerilog module `top` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module top(output logic [31:0] o);
typedef logic [31:0] word;
function automatic word get_abcd();
return 32'hABCD;
endfunction
assign o = get_abcd();
endmodule
... |
<think>
* DUT: `top` module.
* Functionality: Output `o` should always be `32'hABCD`.
* Test Plan: Constant value verification. Compare `o` with `32'hABCD`.
* Requirements:
* Instantiate as `uut`.
* Self-checking (assertions/fatals).
* Compatible with `iverilog -g2012`... | top | uut |
Read the SystemVerilog module `VerilogA` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module VerilogA
(
input a,
output aa
);
assign aa = a;
endmodule : VerilogA
```
# Test Plan: VerilogA
## 1. Functional Intent
The `VerilogA` mo... |
<think>
* DUT: `VerilogA` (input `a`, output `aa`, logic: `assign aa = a`).
* Goal: Self-checking SystemVerilog testbench.
* Requirements:
* Follow the Test Plan.
* Instantiate DUT as `tb_top` (Wait, the prompt says "The DUT will be instantiated as `tb_top`", but usually the *top modu... | VerilogA | tb_top |
Read the SystemVerilog module `top` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// Pedro Manoel
// Lista HDL: Lógica combinatória
parameter divide_by=100000000; // divisor do clock de referência
// A frequencia do clock de referencia é 50 MHz.
// A frequenc... |
<think>
* DUT: `top` module.
* Inputs: `clk_2` (unused but requested), `SWI` (8 bits).
* Outputs: `LED` (8 bits), `SEG` (8 bits), `lcd_a`, `lcd_b`, `lcd_instruction`, `lcd_registrador` (array), `lcd_pc`, `lcd_SrcA`, `lcd_SrcB`, `lcd_ALUResult`, `lcd_Result`, `lcd_WriteData`, `lcd_ReadData`, `lcd_MemWrite... | top | tb_top |
Read the SystemVerilog module `altera_std_synchronizer_nocut` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
// (C) 2001-2022 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// soft... |
<think>
* Module Name: `altera_std_synchronizer_nocut`
* Purpose: Single-bit clock domain crossing (CDC) synchronizer.
* Functionality: A chain of flip-flops (shift register) to mitigate metastability.
* Parameters:
* `depth` (default 3): Number of stages. Must be $\ge 2$.
* `rs... | altera_std_synchronizer_nocut | test_altera_std_synchronizer_nocut |
Read the SystemVerilog module `k1_ZTS13MMstv3_cplusd_bb_ZTS13MMstv3_cplusd_B4_sr_0` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// -------------------------------------------------------------------------
// High Level Design Compiler for Intel(R) FPGAs Vers... |
<think>
* DUT: `k1_ZTS13MMstv3_cplusd_bb_ZTS13MMstv3_cplusd_B4_sr_0`.
* Function: 1-deep skid buffer (registered bypass).
* Inputs: `in_i_stall`, `in_i_valid`, `in_i_data_0_tpl`, `clock`, `resetn`.
* Outputs: `out_o_stall`, `out_o_valid`, `out_o_data_0_tpl`.
* Key Logic:
* `combined... | k1_ZTS13MMstv3_cplusd_bb_ZTS13MMstv3_cplusd_B4_sr_0 | uut |
Read the SystemVerilog module `trigterm_4bit` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module trigterm_4bit (
input wire [3:0] in_data,
input wire clk,
input wire wrenb,
input wire din,
output wire [3:0] out_data,
output w... |
<think>
* DUT: `trigterm_4bit`.
* Inputs: `in_data [3:0]`, `clk`, `wrenb`, `din`.
* Outputs: `out_data [3:0]`, `hit`.
* Logic:
* `wrenb == 1`: `out_data <= in_data`, `hit <= (in_data >= 0 && in_data <= 15)` (always 1 for 4-bit).
* `wrenb == 0`: `out_data <= din` (zero-extended),... | trigterm_4bit | test_trigterm_4bit |
Read the SystemVerilog module `alu` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module alu (
input logic [7:0] a, b,
input bit [1:0] s,
output logic [8:0]y
);
always_comb begin
case (s)
2'b00: y = a | b; // OR
2'b01: y = a & b; // AND... |
<think>
* DUT: `alu` (Combinational, 8-bit inputs `a`, `b`, 2-bit op select `s`, 9-bit output `y`).
* Operations: 00: OR, 01: AND, 10: ADD, 11: SUB.
* Requirements:
* Self-checking.
* Reference model.
* Directed tests (Logic, Add, Sub boundary cases).
* Random test... | alu | alu_tb |
Read the SystemVerilog module `accelerator_design` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
////////////////////////////////////////////////////////////////////////////////
// __ _ _ _ //
//... |
<think>
* DUT: `accelerator_design` (8-bit adder, registered output).
* Inputs: `clk`, `rst`, `in1` (8-bit), `in2` (8-bit).
* Output: `out` (9-bit).
* Behavior: `out <= in1 + in2` on rising edge of `clk`, async reset `rst` to 0.
* Constraints: Compatible with `iverilog -g2012`. No classes, no... | accelerator_design | tb_top |
Read the SystemVerilog module `k0_ZTS6MMstv3_ZTS6MMstv3_B0_branch` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// -------------------------------------------------------------------------
// High Level Design Compiler for Intel(R) FPGAs Version 2021.3 (Relea... |
<think>
* DUT: `k0_ZTS6MMstv3_ZTS6MMstv3_B0_branch`
* Inputs: `in_stall_in_0` (1-bit), `in_valid_in` (1-bit), `clock` (1-bit), `resetn` (1-bit).
* Outputs: `out_stall_out` (1-bit), `out_valid_out_0` (1-bit).
* Logic:
* `out_valid_out_0 = in_valid_in`
* `out_stall_out = in_valid_... | k0_ZTS6MMstv3_ZTS6MMstv3_B0_branch | test_k0_ZTS6MMstv3_ZTS6MMstv3_B0_branch |
Read the SystemVerilog module `tile_controller` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// =============================================================================
// Module : tile_controller
// Purpose : Top-level sequencer for the BitNet b1.58 a... |
<think>
* DUT: `tile_controller`.
* Purpose: Sequence BRAM read addresses, handle pipeline drain (12 cycles), signal completion.
* FSM: IDLE $\to$ COMPUTE $\to$ DRAIN $\to$ IDLE.
* Inputs: `clk`, `rst_n`, `start_inference`, `total_tiles`.
* Outputs: `bram_read_addr`, `array_en`, `inference_do... | tile_controller | tile_controller_tb |
Read the SystemVerilog module `som_system_error_adapter_180_ww4pkiq` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software a... |
<think>
* DUT: `som_system_error_adapter_180_ww4pkiq`.
* Inputs: `clk`, `reset_n`, `in_valid`, `in_data` [33:0], `out_ready`.
* Outputs: `in_ready`, `out_valid`, `out_data` [33:0], `out_error` [0:0].
* Logic: Combinational pass-through.
* `in_ready = out_ready`
* `out_valid = in... | som_system_error_adapter_180_ww4pkiq | test_som_system_error_adapter_180_ww4pkiq |
Read the SystemVerilog module `top_module` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module top_module(
input a,
input b,
input sel_b1,
input sel_b2,
output reg out_always
);
always @(*) begin
case ({sel_b2, sel_b1})
... |
<think>
* DUT: `top_module` (combinational 2-to-1 MUX based on `sel_b2`).
* Inputs: `a`, `b`, `sel_b1`, `sel_b2` (all 1-bit).
* Output: `out_always` (1-bit).
* Functional Intent: `out_always = (sel_b2 == 0) ? a : b`. `sel_b1` is ignored.
* Test Strategy: Exhaustive testing (16 combinations).
... | top_module | top_module_verif_tb |
Read the SystemVerilog module `sync` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
//These are synchronizers required for bringing asynchronous signals into the FPGA
//synchronizer with no reset (for switches/buttons)
module sync (
input log... |
<think>
* Input: Three small SystemVerilog modules: `sync` (basic DFF), `sync_r0` (DFF with async reset to 0), `sync_r1` (DFF with async reset to 1).
* Goal: Write a test plan for a SV testbench to verify these modules.
* Constraints: Use `dut` as instance name, `iverilog -g2012` compatible, markdown for... | sync | dut |
Read the SystemVerilog module `sum_module` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
module sum_module (
input clk,
input reset,
input [3:0] data_in,
output reg [1:0] data_out
);
always @(posedge clk) begin
if (rese... |
<think>
* Module: `sum_module`.
* Inputs: `clk`, `reset`, `data_in[3:0]`.
* Outputs: `data_out[1:0]`.
* Logic:
* Synchronous reset: `data_out <= 0`.
* Condition: If `data_in[3:2] >= 2` (essentially, if `data_in[3:2] == 2'b10` or `2'b11`), then `data_out <= data_in[1:0] + 1`.
... | sum_module | tb_top |
Read the SystemVerilog module `mux_4x1` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
module mux_4x1
(
input logic [31:0] in_0,
input logic [31:0] in_1,
input logic [31:0] in_2,
input logic [31:0] in_3,
input logic [ 1:0] s... |
<think>
* DUT: `mux_4x1`.
* Inputs: four 32-bit data inputs (`in_0`, `in_1`, `in_2`, `in_3`) and one 2-bit select line (`select_line`).
* Output: one 32-bit output (`out`).
* Logic: Combinational `always_comb` with a `case` statement. It's a simple 4-to-1 multiplexer.
* Functional intent: Ro... | mux_4x1 | tb |
Read the SystemVerilog module `Device` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
`default_nettype none
module Device(
input logic [7:0] doubleNibble,
output logic [3:0] sum
);
// I would probably write the example instance2, but t... |
<think>
* Top module: `Device`
* Inputs: `doubleNibble [7:0]`
* Outputs: `sum [3:0]`
* Implementation:
* It uses a `Helper` module.
* `instance1`: Takes `doubleNibble[7:4]` (high nibble) and `doubleNibble[3:0]` (low nibble) and outputs the sum to `sum`.
* `instance2`: ... | Device | tb_top |
Read the SystemVerilog module `accelerator_design` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
////////////////////////////////////////////////////////////////////////////////
// __ _ _ _ ... |
<think>
* Module: `accelerator_design`
* Inputs: `clk`, `rst`, `in1` (8-bit), `in2` (8-bit).
* Output: `out` (9-bit).
* Functionality: A simple synchronous adder. On `rst`, `out` is 0. Otherwise, on every `posedge clk`, `out` captures `in1 + in2`.
* Complexity: Very low.
* Functional I... | accelerator_design | tb_accelerator_design |
Read the SystemVerilog module `slavereg_comp_B0_runOnce_merge` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// -------------------------------------------------------------------------
// High Level Design Compiler for Intel(R) FPGAs Version 21.1 (Release Bui... |
<think>
* DUT: `slavereg_comp_B0_runOnce_merge`
* Inputs: `in_stall_in` (1 bit), `in_valid_in_0` (1 bit), `clock`, `resetn`.
* Outputs: `out_stall_out_0` (1 bit), `out_valid_out` (1 bit).
* Logic:
* `out_valid_out = in_valid_in_0`
* `out_stall_out_0 = in_valid_in_0 & in_stall_in... | slavereg_comp_B0_runOnce_merge | slavereg_comp_B0_runOnce_merge_test |
Read the SystemVerilog module `rom` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
module rom(
input logic [3:0] addr,
output logic [7:0] data
);
always_comb begin
case (addr) // addr data assembler
4'b0000: d... |
<think>
* Module: `rom`
* Input: `addr [3:0]` (4 bits)
* Output: `data [7:0]` (8 bits)
* Logic: Combinational `always_comb` block with a `case` statement.
* Contents:
* `0` -> `8'h60`
* `1` -> `8'h90`
* `2` -> `8'h3D`
* `3` -> `8'h01`
* `4` ->... | rom | tb_rom |
Read the SystemVerilog module `STD_WRAP_CKINV` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
// ----------------------------------------------------------------------
// Copyright 2024 TimingWalker
//
// Licensed under the Apache License, Version 2... |
<think>
* Module name: `STD_WRAP_CKINV`
* Inputs: `in_i` (1 bit)
* Outputs: `zn_o` (1 bit)
* Functionality: `zn_o = ~in_i`.
* It's a simple inverter (NOT gate).
* There is a conditional compilation (`ifdef ASIC`), but in both cases, the behavior is the same: `zn_o = ~in_i`.
* Com... | STD_WRAP_CKINV | tb |
Read the SystemVerilog module `accelerator_design` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
////////////////////////////////////////////////////////////////////////////////
// __ _ _ _ ... |
<think>
* DUT: `accelerator_design`
* Inputs: `clk`, `rst`, `in1` (8-bit), `in2` (8-bit).
* Output: `out` (9-bit).
* Logic: A registered adder. `out <= in1 + in2` on the positive edge of the clock, provided `rst` is low.
* Reset: Asynchronous positive edge reset (`posedge rst`). Resets `out` ... | accelerator_design | tb_accelerator_design |
Read the SystemVerilog module `syncronizer` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
module syncronizer #(parameter RESET_VALUE = 0) (
input logic clk_i,
input logic rst_n_i,
input logic async_sign_i,
output logic sync... |
<think>
* Module Name: `syncronizer` (spelled as "syncronizer", not "synchronizer").
* Purpose: A classic 2-stage flip-flop synchronizer to handle asynchronous input signals and prevent metastability in the destination clock domain.
* Parameters: `RESET_VALUE` (default 0). Sets initial state of the 2-sta... | syncronizer | syncronizer_test |
Read the SystemVerilog module `k0_ZTS6MMstv2_readdata_reg_unnamed_33_k0_ZTS6MMstv26` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
// -------------------------------------------------------------------------
// High Level Design Compiler for Intel... |
<think>
* Module Name: `k0_ZTS6MMstv2_readdata_reg_unnamed_33_k0_ZTS6MMstv26`
* Inputs: `in_stall_in`, `in_data_in[31:0]`, `in_valid_in`, `clock`, `resetn`.
* Outputs: `out_stall_out`, `out_data_out[31:0]`, `out_valid_out`.
* *Registers:*
* `readdata_reg_unnamed_..._data_reg_q`: 32-bit r... | k0_ZTS6MMstv2_readdata_reg_unnamed_33_k0_ZTS6MMstv26 | k0_ZTS6MMstv2_readdata_reg_unnamed_33_k0_ZTS6MMstv26_tb |
Read the SystemVerilog module `rotator_mux` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module rotator_mux(
input clk,
input load,
input [1:0] ena,
input [99:0] data,
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
inpu... |
<think>
* DUT: `rotator_mux`
* Functionality 1 (Sequential): 100-bit shift register (`shift_reg`).
* Priority: `load` > `ena[0]` (Rotate Left) > `ena[1]` (Rotate Right).
* Functionality 2 (Combinational): Mux and Formatter.
* `sel` (3-bit) selects from `data0` to `data5` (4-bit). `sel... | rotator_mux | rotator_mux_verif_tb |
Read the SystemVerilog module `k0_ZTS9MMpara_v1_ZTS9MMpara_v1_B0_branch` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// -------------------------------------------------------------------------
// High Level Design Compiler for Intel(R) FPGAs Version 20.4 (R... |
<think>
* DUT: `k0_ZTS9MMpara_v1_ZTS9MMpara_v1_B0_branch`
* Logic:
* `out_acl_global_id_0 = in_acl_global_id_0`
* `out_acl_global_id_1 = in_acl_global_id_1`
* `out_valid_out_0 = in_valid_in`
* `out_stall_out = in_valid_in & in_stall_in_0`
* Interface:
* I... | k0_ZTS9MMpara_v1_ZTS9MMpara_v1_B0_branch | k0_ZTS9MMpara_v1_ZTS9MMpara_v1_B0_branch_test |
Read the SystemVerilog module `decoder` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
//
// Instruction decoder for micro-BESM
//
// Copyright (c) 2016 Serge Vakulenko
//
// Permission is hereby granted, free of charge, to any person obtaining a co... |
<think>
* Module: `decoder`.
* Inputs: `dc` (64:1), `pe` (1), `tkk` (1).
* Outputs: `ir` (3:0), `op` (7:0), `extop` (1), `ir15` (1), `addr` (19:0).
* Logic: Purely combinational. No clock, no reset.
* Behavior:
* `ir` (modifier index): Depends on `pe` and `tkk`.
* `ir15`: ... | decoder | dut |
Read the SystemVerilog module `k0_ZTS6MMstv2_ZTS6MMstv2_B3_branch` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
// -------------------------------------------------------------------------
// High Level Design Compiler for Intel(R) FPGAs Version ... |
<think>
`k0_ZTS6MMstv2_ZTS6MMstv2_B3_branch`.
A set of data registers (64-bit and 1-bit) and some control logic involving `valid` and `stall` signals.
* `in_valid_in`: Global valid signal.
* `in_c0_exe15`: A steering/branch signal.
* `in_stall_in_0` and `in_stall_in_1`: Backpressure sign... | k0_ZTS6MMstv2_ZTS6MMstv2_B3_branch | test_k0_ZTS6MMstv2_ZTS6MMstv2_B3_branch |
Read the SystemVerilog module `accelerator_design` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
////////////////////////////////////////////////////////////////////////////////
// __ _ _ _ ... |
<think>
* Module Name: `accelerator_design`.
* Inputs: `clk`, `rst` (asynchronous active-high reset), `in1[7:0]`, `in2[7:0]`.
* Output: `out[8:0]`.
* Functionality: Synchronous addition of two 8-bit numbers, result is a 9-bit number.
* Behavior:
* Reset: `out` becomes 0.
* ... | accelerator_design | dut |
Read the SystemVerilog module `clock_gen` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module clock_gen (
clk,
reset,
frequency,
clk_out
);
parameter DDS_PRESCALE_NDIV_P... |
<think>
* DUT: `clock_gen` (a DDS-based clock generator).
* Purpose: Generate a pulse-train `clk_out` based on `frequency` input.
* Logic:
* Prescaler: `clk` $\rightarrow$ `dds_clk` (divided by 5).
* Phase Accumulator: `dds_phase` increments by `frequency` when `dds_clk` is high.
... | clock_gen | clock_gen_verif_tb |
Read the SystemVerilog module `sky130_fd_sc_lp__a2bb2o` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
module sky130_fd_sc_lp__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output X ;
input A1_N;
inpu... |
<think>
* Module Name: `sky130_fd_sc_lp__a2bb2o`
* Inputs: `A1_N`, `A2_N`, `B1`, `B2` (all 1-bit)
* Outputs: `X` (1-bit)
* Internal Logic:
* `and0_out = B1 & B2`
* `nor0_out = ~(A1_N | A2_N)`
* `or0_out_X = nor0_out | and0_out`
* `X = or0_out_X` (via buffer)
... | sky130_fd_sc_lp__a2bb2o | tb_top |
Read the SystemVerilog module `accelerator_design` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
////////////////////////////////////////////////////////////////////////////////
// __ _ _ _ //
//... |
<think>
* DUT: `accelerator_design` (8-bit unsigned adder, 9-bit registered output, asynchronous active-high reset).
* Test Plan Requirements:
* Reference Model: `expected_out = in1 + in2` (with 1-cycle latency).
* Invariants: Range check $[0, 510]$, Reset priority.
* Scenarios: P... | accelerator_design | dut |
Read the SystemVerilog module `wt_mem4` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
/*
Copyright 2019, Grant Yu
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as publishe... |
<think>
* Module Name: `wt_mem4`
* Parameters: `ADDR_WIDTH = 7`, `DATA_WIDTH = 144`, `DEPTH = 76`.
* Inputs: `clk`, `addr_a`, `addr_b`.
* Outputs: `q_a`, `q_b`.
* Internal Structure: A memory array `mem` of size `DEPTH` x `DATA_WIDTH`.
* Initialization: `initial` block loads 76 hard-cod... | wt_mem4 | uut |
Read the SystemVerilog module `accelerator_design` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
////////////////////////////////////////////////////////////////////////////////
// __ _ _ _ //
//... |
<think>
* DUT: `accelerator_design` (an 8-bit unsigned registered adder).
* Inputs: `clk`, `rst`, `in1` [7:0], `in2` [7:0].
* Output: `out` [8:0].
* Behavior: `out <= in1 + in2` on `posedge clk` or `out <= 0` on `posedge rst`.
* Key Detail: 1-cycle latency.
* Reference Model: `expected... | accelerator_design | tb_top |
Read the SystemVerilog module `top` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module top(output int o);
parameter int MuBi4Width = 4;
typedef enum logic [MuBi4Width-1:0] {
MuBi4Hi = 4'h5,
MuBi4Lo = 4'hA
} mubi4_e;
function automati... |
<think>
* DUT: `top` module.
* Functionality: Returns a constant integer `o` which is the result of casting `MuBi4Hi` (4'h5) to an `int`.
* Expected Output: `o = 5`.
* Requirement: Self-checking SystemVerilog testbench, compatible with `iverilog -g2012`.
* Specific constraints:
* In... | top | dut |
Read the SystemVerilog module `barrel_shifter_4bit` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
module barrel_shifter_4bit (
input [3:0] data_in,
input [3:0] shift_amount,
output reg [3:0] data_out
);
always @(*) begin
if... |
<think>
* Module: `barrel_shifter_4bit`
* Inputs: `data_in[3:0]`, `shift_amount[3:0]`
* Output: `data_out[3:0]`
* Logic:
* `if (shift_amount >= 0) data_out = data_in << shift_amount;`
* `else data_out = data_in >> (-shift_amount);`
* *Crucial Observation:* `shift_amount` i... | barrel_shifter_4bit | test_barrel_shifter_4bit |
Read the SystemVerilog module `vga_demo` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
module vga_demo
(
CLOCK_PIXEL,
RESET,
VGA_RED,
VGA_GREEN,
VGA_BLUE,
VGA_HS,
VGA_VS,
BLANK_... |
<think>
Expert SystemVerilog Verification Engineer.
`vga_demo` module.
Write a comprehensive test plan for a SystemVerilog testbench.
`test_vga_demo`.
Markdown, wrapped in `<TEST_PLAN>` tags.
Design functionality, port semantics, test scenarios, verification techniques (golden model, invariants, etc.).
* *Input... | vga_demo | test_vga_demo |
Read the SystemVerilog module `mux4to1` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module mux4to1 (
input A,
input B,
input C,
input D,
input S0,
input S1,
output Y,
input VDD,
input VSS
);
assign Y = (S1 & S0 & D... |
<think>
* DUT: `mux4to1`.
* Inputs: `A`, `B`, `C`, `D`, `S0`, `S1`, `VDD`, `VSS`.
* Output: `Y`.
* Logic: `Y = (S1&S0&D) | (S1&~S0&C) | (~S1&S0&B) | (~S1&~S0&A)`.
* Test Plan Goals:
* Reference model based on the truth table.
* Exhaustive combinatorial sweep ($2^8 = 256$ c... | mux4to1 | mux4to1_test |
Read the SystemVerilog module `tx_inv` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
module tx_inv (
input wire logic DIN,
output wire DOUT
);
assign DOUT = ~(DIN);
endmodule
```
Cover the functional intent, port semantics, verification... |
<think>
* Module: `tx_inv`
* Function: Simple inverter. `DOUT = ~DIN`.
* Inputs: `DIN` (1 bit).
* Outputs: `DOUT` (1 bit).
* Type: Combinational logic. No clock, no reset, no parameters.
* Functional intent: Invert the input signal.
* Port semantics: `DIN` is the source, `DOUT` i... | tx_inv | tx_inv_verif_tb |
Read the SystemVerilog module `forwarding_unit` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module forwarding_unit (
input ex_inPortSelect,
input mem_inPortSelect,
input [2:0] ex_mem_rdest,
input ex_mem_reg_write,
input [3:0] mem_wb_rdes... |
<think>
* Design Under Test (DUT): `forwarding_unit`.
* Functionality: A combinational block for hazard detection/forwarding in a pipeline.
* Inputs: `ex_inPortSelect`, `mem_inPortSelect`, `ex_mem_rdest` (3b), `ex_mem_reg_write`, `mem_wb_rdest` (4b), `mem_wb_reg_write`, `rsrc` (4b), `rdest` (4b).
* ... | forwarding_unit | tb_forwarding_unit |
Read the SystemVerilog module `jtag_pll_master_0_timing_adt` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// (C) 2001-2020 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools... |
<think>
* DUT: `jtag_pll_master_0_timing_adt`
* Functionality: Combinational pass-through. `out_valid = in_valid`, `out_data = in_data`.
* Inputs: `clk`, `reset_n`, `in_valid`, `in_data`, `out_ready`.
* Outputs: `out_valid`, `out_data`.
* Key Insight: `clk`, `reset_n`, and `out_ready` have no... | jtag_pll_master_0_timing_adt | dut |
Read the SystemVerilog module `binary_to_gray` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
module binary_to_gray
#(parameter WIDTH=4)
(input logic [WIDTH-1:0] b_in,
output logic [WIDTH-1:0] g_out);
always_comb begin
g_out[WIDTH-1... |
<think>
* Module: `binary_to_gray`
* Parameter: `WIDTH` (default 4)
* Inputs: `b_in` (binary input)
* Outputs: `g_out` (Gray code output)
* Logic:
* `g_out[WIDTH-1] = b_in[WIDTH-1]` (MSB remains the same)
* `g_out[i-1] = b_in[i] ^ b_in[i-1]` for `i` from `WIDTH-1` down to ... | binary_to_gray | uut |
Read the SystemVerilog module `soc_system_mm_interconnect_0_cmd_demux` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software... |
<think>
* DUT: `soc_system_mm_interconnect_0_cmd_demux`.
* Inputs: `sink_valid` (2 bits), `sink_data` (229 bits), `sink_channel` (2 bits), `sink_startofpacket`, `sink_endofpacket`, `src0_ready`, `src1_ready`, `clk`, `reset`.
* Outputs: `sink_ready`, `src0_valid`, `src0_data` (229 bits), `src0_channel` (2... | soc_system_mm_interconnect_0_cmd_demux | uut |
Read the SystemVerilog module `adder_8bit` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module adder_8bit(
input [7:0] A,
input [7:0] B,
output [7:0] sum,
output carry_out
);
wire[8:0] temp_sum;
assign temp_sum = {1'b0, A} + {1'b0, B}... |
<think>
* Design: `adder_8bit` (combinational 8-bit adder).
* Inputs: `A [7:0]`, `B [7:0]`.
* Outputs: `sum [7:0]`, `carry_out`.
* Goal: Self-checking testbench based on a specific test plan.
* Requirements:
* DUT instance name: `uut`.
* Directed test cases (Zero, Identity... | adder_8bit | uut |
Read the SystemVerilog module `Computer_System_mm_interconnect_0_avalon_st_adapter_009_error_adapter_0` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design... |
<think>
* Module Name: `Computer_System_mm_interconnect_0_avalon_st_adapter_009_error_adapter_0`
* Purpose: It's an Avalon Streaming Error Adapter.
* Logic analysis:
* `in_ready = out_ready` (Combinational)
* `out_valid = in_valid` (Combinational)
* `out_data = in_data` (Com... | Computer_System_mm_interconnect_0_avalon_st_adapter_009_error_adapter_0 | Computer_System_mm_interconnect_0_avalon_st_adapter_009_error_adapter_0_verif_tb |
Read the SystemVerilog module `bitwise_xor` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
module bitwise_xor(input [7:0] A, input [7:0] B, input C, output reg [7:0] Y);
always @(*) begin
if(C) begin
Y = A ^ B;
end
else begin
... |
<think>
* Module Name: `bitwise_xor`
* Inputs: `A` (8-bit), `B` (8-bit), `C` (1-bit control).
* Output: `Y` (8-bit).
* Logic:
* If `C == 1`, `Y = A ^ B`.
* If `C == 0`, `Y = A`.
* Nature: Purely combinational (no clock, no reset).
* Expert SystemVerilog Verification... | bitwise_xor | tb |
Read the SystemVerilog module `accelerator_design` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
////////////////////////////////////////////////////////////////////////////////
// __ _ _ _ ... |
<think>
* Top module: `accelerator_design`.
* Inputs: `clk` (1), `rst` (1), `in1` (8), `in2` (8).
* Output: `out` (9).
* Functionality: On `posedge clk`, `out` becomes `in1 + in2`.
* Reset: Asynchronous `posedge rst` resets `out` to 0.
* Design is a simple synchronous adder with an asyn... | accelerator_design | tb_accelerator_design |
Read the SystemVerilog module `uart_tx` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
// Based on Module by : Yuya Kudo
module uart_tx #(parameter
DATA_WIDTH = 8,
BAUD_RATE = 115_200,
CLK_FREQ = 50_000_000,
localparam
LB_DATA_... |
<think>
* Module: `uart_tx`
* Purpose: Transmit data serially via UART.
* Parameters: `DATA_WIDTH` (8), `BAUD_RATE` (115,200), `CLK_FREQ` (50 MHz).
* Calculated values: `PULSE_WIDTH` (CLK_FREQ / BAUD_RATE), `PULSE_AND_HALF` (1.5 * PULSE_WIDTH).
* Inputs: `clk`, `tx_data`, `tx_valid`, `reset_n... | uart_tx | tb_top |
Read the SystemVerilog module `soc_system_mm_interconnect_1_rsp_demux_001` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// (C) 2001-2020 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// soft... |
<think>
* DUT: `soc_system_mm_interconnect_1_rsp_demux_001`
* Function: Combinational demultiplexer.
* Inputs: `sink_valid`, `sink_data` (125b), `sink_channel` (4b), `sink_startofpacket`, `sink_endofpacket`.
* Outputs: `sink_ready`, and three source interfaces (`src0`, `src1`, `src2`) with `valid`,... | soc_system_mm_interconnect_1_rsp_demux_001 | uut |
Read the SystemVerilog module `timer` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module timer(
input clk,
input rst,
output logic [31:0] cycle_count
);
always @(posedge clk) begin
if (rst)
cycle_count <= 0;
else
... |
<think>
* DUT: `timer` module.
* Inputs: `clk`, `rst`.
* Output: `cycle_count [31:0]`.
* Logic: Synchronous reset to 0; otherwise increments by 1 each clock cycle.
* Goal: Comprehensive self-checking testbench.
* Reference Model: `expected_count` mirror.
* Invariants: Reset prior... | timer | timer_verif_tb |
Read the SystemVerilog module `accelerator_design` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
////////////////////////////////////////////////////////////////////////////////
// __ _ _ _ ... |
<think>
* DUT Name: `accelerator_design`
* Inputs: `clk`, `rst`, `in1[7:0]`, `in2[7:0]`
* Output: `out[8:0]`
* Functionality: A simple synchronous adder.
* Logic:
* `rst` is asynchronous (posedge).
* On `rst`, `out` becomes 0.
* On `clk` posedge, `out` becomes `i... | accelerator_design | tb |
Read the SystemVerilog module `top_module` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module nor_gate (
input a,
input b,
output out
);
assign out = !(a & b);
endmodule
module full_adder (
input a,
input b,
input cin,
output... |
<think>
* DUT: `top_module` (combinational logic).
* Sub-modules: `nor_gate` (actually NAND), `full_adder` (modified `cout`), `bitwise_and` (specific masking).
* Goal: Self-checking testbench following a specific test plan.
* Test Plan Requirements:
* Reference Model: `ref_sum = a ^ b ^ c... | top_module | tb |
Read the SystemVerilog module `multiplier_module` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
module multiplier_module (
i_data0,
o_data0
);
// Port mode declarations:
input [15:0] i_data0;
output [15:0] o_data0;
//Multiplier... |
<think>
* Module: `multiplier_module`
* Input: `i_data0` (16 bits)
* Output: `o_data0` (16 bits)
* Internal logic:
* `w1 = i_data0`
* `w2` through `w16` are shifts of `w1` (from `<< 1` to `<< 15`).
* `o_data0 = sum of w1 through w16`.
* Mathematical equivalence: ... | multiplier_module | tb_multiplier_module |
Read the SystemVerilog module `wb_stagging` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
//////////////////////////////////////////////////////////////////////////////
// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
//
... |
<think>
`wb_stagging` (Wishbone Staging).
Provide a holding register (staging flip-flops) for a Wishbone interface to break timing issues.
Staging FFs introduce a delay. Continuous bursts will have a one-cycle gap between transactions.
* *Master Interface (Input to DUT):* `m_wbd_*_i`
* *Master Int... | wb_stagging | wb_stagging_test |
Read the SystemVerilog module `FA` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
///////////////////////////////////////////////////
// FA.sv This design will take in 3 bits //
// and add them to produce a sum and carry out //
///////////... |
<think>
* Module Name: `FA` (Full Adder).
* Inputs: `A`, `B`, `Cin` (all 1-bit).
* Outputs: `S` (Sum), `Cout` (Carry out).
* Logic Implementation: Structural Verilog using `xor`, `and`, and `or` gates.
* Functionality: Standard Full Adder logic.
* $S = A \oplus B \oplus Cin$
... | FA | test_FA |
Read the SystemVerilog module `bidirectional_data_port` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module bidirectional_data_port (
input clk,
input reset,
input [7:0] data_in,
input direction_control,
output reg [7:0] data_out
);
always @(posed... |
<think>
* DUT: `bidirectional_data_port`.
* Inputs: `clk`, `reset`, `data_in[7:0]`, `direction_control`.
* Output: `data_out[7:0]`.
* Logic:
* Reset (async high) $\rightarrow$ `data_out = 0`.
* `direction_control == 1` $\rightarrow$ `data_out = data_in` (on posedge clk).
... | bidirectional_data_port | bidirectional_data_port_verif_tb |
Read the SystemVerilog module `adder` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module full_adder (
A,
B,
CIN,
SUM,
COUT
);
input A;
input B;
input CIN;
output SUM;
output COUT;
assign SUM = A ^ B ^ CIN;
ass... |
<think>
* DUT: `adder` (4-bit ripple carry adder).
* Inputs: `A` [3:0], `B` [3:0], `CIN`.
* Outputs: `SUM` [3:0], `COUT`, `VPWR` (const 1), `VGND` (const 0).
* Verification Goal: Self-checking testbench.
* Requirements:
* Reference model: `(A + B + CIN)`.
* Invariants: `VP... | adder | tb_top |
Read the SystemVerilog module `blinkled_mm_interconnect_0_rsp_demux` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software... |
<think>
* DUT: `blinkled_mm_interconnect_0_rsp_demux`.
* Functionality: A combinational demultiplexer. Routes `sink` inputs to `src0` outputs based on `sink_channel[0]`.
* Interfaces:
* Sink: `sink_valid`, `sink_data` (96 bits), `sink_channel` (6 bits), `sink_startofpacket`, `sink_endofpacket`,... | blinkled_mm_interconnect_0_rsp_demux | dut |
Read the SystemVerilog module `controller_mm_interconnect_2_router_001` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
// (C) 2001-2020 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and othe... |
<think>
Expert SystemVerilog Verification Engineer.
`controller_mm_interconnect_2_router_001`.
Write a comprehensive test plan for another engineer to build a SV testbench.
* DUT name in TB: `controller_mm_interconnect_2_router_001_test`.
* Toolchain: `iverilog -g2012`.
* Output format: ... | controller_mm_interconnect_2_router_001 | controller_mm_interconnect_2_router_001_test |
Read the SystemVerilog module `prim_count` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module prim_count #(
parameter int Width = 1
) (
input logic clk_i,
input logic rst_ni,
input logic clr_i,
input logic ... |
<think>
* DUT: `prim_count`.
* Parameters: `Width`.
* Inputs: `clk_i`, `rst_ni`, `clr_i`, `set_i`, `set_cnt_i`, `incr_en_i`, `decr_en_i`, `step_i`, `commit_i`.
* Outputs: `cnt_o`, `cnt_after_commit_o`, `err_o`.
* Logic:
* `cnt_n` (combinational):
* `clr_i` (priority 1)... | prim_count | prim_count_verif_tb |
Read the SystemVerilog module `accelerator_design` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
////////////////////////////////////////////////////////////////////////////////
// __ _ _ _ ... |
<think>
* DUT: `accelerator_design`
* Inputs: `clk`, `rst`, `in1[7:0]`, `in2[7:0]`
* Outputs: `out[8:0]`
* Logic: Synchronous addition of two 8-bit inputs with a 9-bit output (to prevent overflow).
* Reset: Asynchronous positive-edge reset (`posedge rst`). When `rst` is high, `out` is 0.
... | accelerator_design | dut |
Read the SystemVerilog module `fetch` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
`default_nettype none
module fetch(clk, reset, stall, pc, nextpc, mispred, commit_pc);
input wire clk, reset, stall;
output logic [31:0] pc, nextpc;
input wire mispred;
... |
<think>
* Module: `fetch`
* Inputs: `clk`, `reset`, `stall`, `mispred`, `commit_pc`
* Outputs: `pc`, `nextpc`
* Behavior:
* `nextpc = (mispred) ? commit_pc : pred_pc` (combinational).
* On `posedge clk`:
* If `reset`: `pc <= 0`, `pred_pc <= 4`.
* Else... | fetch | tb |
Read the SystemVerilog module `dut` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
// +FHDR----------------------------------------------------------------------------
// Project Name : IC_Design
// Device : ASIC
// Author : zhouyuqia... |
<think>
* Top module: `dut`
* Inputs: `clk`, `rst_n`, `rxd` [7:0], `rx_dv`.
* Outputs: `txd` [7:0], `tx_en`.
* Logic: Synchronous reset (`!rst_n`). On `posedge clk`, `txd` gets `rxd` and `tx_en` gets `rx_dv`.
* Essentially, it's a 1-cycle delay (pipeline stage) for the data and the valid sign... | dut | tb_dut |
Read the SystemVerilog module `accelerator_design` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
////////////////////////////////////////////////////////////////////////////////
// __ _ _ _ //
//... |
<think>
* DUT: `accelerator_design`
* Inputs: `clk`, `rst`, `in1` (8-bit), `in2` (8-bit).
* Output: `out` (9-bit).
* Functionality: Synchronous 8-bit unsigned adder (`out <= in1 + in2`). Asynchronous active-high reset (`out <= 0`).
* Reference Model: `expected_out = in1 + in2`.
* Verif... | accelerator_design | tb_accelerator_design |
Read the SystemVerilog module `dff` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
/* ==============================================================
File: dff.sv
Author: Rey Gomez
Date: 2026-04-1
Usage: D-Flip-Flop
Summary:
=====================... |
<think>
* Design: `dff` (D-Flip-Flop).
* Inputs: `clk`, `d`.
* Output: `q`.
* Behavior: Positive-edge triggered flip-flop (`always_ff @(posedge clk) q <= d;`).
* Crucial Observation: There is **no reset** signal.
* Expert SystemVerilog Verification Engineer.
* Task: Write a test ... | dff | tb |
Read the SystemVerilog module `soc_system_mm_interconnect_0_router` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software an... |
<think>
* DUT: `soc_system_mm_interconnect_0_router`
* Functionality: Combinational router.
* Inputs: `clk`, `reset`, `sink_valid`, `sink_data[228:0]`, `sink_startofpacket`, `sink_endofpacket`, `src_ready`.
* Outputs: `sink_ready`, `src_valid`, `src_data[228:0]`, `src_channel[1:0]`, `src_startofpac... | soc_system_mm_interconnect_0_router | soc_system_mm_interconnect_0_router_verif_tb |
Read the SystemVerilog module `FullAdder` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
/* Full Adder.
*
*/
module FullAdder (
input wire in1,
input wire in2,
input wire ci, // carry in
output wire sum, // sum of 2 bits
output wire co ... |
<think>
* DUT: `FullAdder` (combinational, 3 inputs: `in1`, `in2`, `ci`; 2 outputs: `sum`, `co`).
* Test Plan:
* Exhaustive testing (8 combinations).
* Reference model: `sum = (in1 + in2 + ci)[0]`, `co = (in1 + in2 + ci)[1]`.
* Self-checking: Use assertions or if-statements with `... | FullAdder | tb |
Read the SystemVerilog module `nios_mm_interconnect_0_rsp_demux` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and t... |
<think>
* DUT: `nios_mm_interconnect_0_rsp_demux`.
* Functionality: Combinational demux.
* Inputs: `sink_valid`, `sink_data` (88 bits), `sink_channel` (3 bits), `sink_startofpacket`, `sink_endofpacket`, `src0_ready`, `clk`, `reset`.
* Outputs: `sink_ready`, `src0_valid`, `src0_data` (88 bits), `src... | nios_mm_interconnect_0_rsp_demux | tb_top |
Read the SystemVerilog module `peripheral_design` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
////////////////////////////////////////////////////////////////////////////////
// __ _ _ _ ... |
<think>
* Module Name: `peripheral_design`
* Functionality: A simple 8-bit adder with a registered output.
* Inputs: `clk`, `rst` (asynchronous high), `in1` (8-bit), `in2` (8-bit).
* Output: `out` (9-bit, to accommodate carry).
* Behavior:
* Reset: `out` becomes 0.
* Norma... | peripheral_design | peripheral_design_test |
Read the SystemVerilog module `priority_mux` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
module priority_mux (
input [3:0] in0,
input [3:0] in1,
input [3:0] in2,
input [3:0] in3,
input PRI,
input [1:0] SEL,
output reg ... |
<think>
* Module: `priority_mux`.
* Inputs: `in0`, `in1`, `in2`, `in3` (all 4-bit); `PRI` (1-bit); `SEL` (2-bit).
* Output: `out` (4-bit).
* Logic:
* If `PRI == 1`: Priority-based selection. Priority order: `in3` > `in2` > `in1` > `in0`. Selection is based on whether the input is non-zero... | priority_mux | tb_top |
Read the SystemVerilog module `accelerator_design` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
////////////////////////////////////////////////////////////////////////////////
// __ _ _ _ ... |
<think>
* Module: `accelerator_design`
* Inputs: `clk`, `rst` (asynchronous active-high), `in1` (8-bit), `in2` (8-bit).
* Output: `out` (9-bit).
* Logic: Simple synchronous adder. `out <= in1 + in2`. Reset clears `out` to 0.
* Complexity: Extremely low.
* The design performs an 8-bit u... | accelerator_design | dut |
Read the SystemVerilog module `WriteBack` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module WriteBack(input logic [31:0] A, B, C, input logic [1:0] wb_sel,
output logic [31:0] wdata);
always_comb begin
case (wb_sel)
0: wdata <= A;
1: wdata <= B... |
<think>
* DUT: `WriteBack` module (a 3-to-1 Mux).
* Inputs: `A`, `B`, `C` (32-bit), `wb_sel` (2-bit).
* Output: `wdata` (32-bit).
* Functionality: `wb_sel=0 -> A`, `wb_sel=1 -> B`, `wb_sel=2 -> C`. `wb_sel=3` is undefined (missing `default` in DUT `case`).
* Reference Model: Predict output b... | WriteBack | uut |
Read the SystemVerilog module `crypto_xor_unit` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module crypto_xor_unit (
input wire clk,
input wire rst,
input wire [7:0] key, // Sensitive input key
input wire [7:0] data_in... |
<think>
* DUT: `crypto_xor_unit`
* Function: `result <= data_in ^ key` (registered, 1-cycle delay).
* Reset: Synchronous `rst`, sets `result` to `0`.
* Interface: `clk`, `rst`, `key [7:0]`, `data_in [7:0]`, `result [7:0]`.
* Reference Model: `expected = rst ? 0 : (data_in ^ key)`.
* Sc... | crypto_xor_unit | dut |
Read the SystemVerilog module `counter` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
module counter (
input clk,
input rst,
output reg [3:0] count,
output reg ovf
);
always @(posedge clk) begin
if (rst) begin
count <= 4'b0;
... |
<think>
* Top module: `counter`
* Inputs: `clk`, `rst`
* Outputs: `count` [3:0], `ovf`
* Behavior:
* Synchronous reset (`rst` checked on `posedge clk`).
* If `rst` is high: `count <= 0`, `ovf <= 0`.
* If `rst` is low:
* If `count == 4'hf` (15): `count <= ... | counter | test_counter |
Read the SystemVerilog module `counter` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
module counter #(parameter DATA_WIDTH = 8)
(
// System
input logic clk_i,
input logic rst_ni,
// Control
input logic load_i,
// D... |
<think>
* Module: `counter`
* Parameter: `DATA_WIDTH` (default 8)
* Inputs: `clk_i`, `rst_ni` (active low, asynchronous), `load_i`, `data_i` (width `DATA_WIDTH`)
* Output: `data_o` (width `DATA_WIDTH`)
* Logic:
* Async reset (`!rst_ni`) $\rightarrow$ `q_r = 0`.
* If `load_... | counter | test_counter |
Read the SystemVerilog module `controller_mm_interconnect_0_router_005` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
// (C) 2001-2020 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and othe... |
<think>
* Module Name: `controller_mm_interconnect_0_router_005`
* Function: A "Merlin Router". It routes packets based on a destination ID.
* Logic:
* Input side: `sink_*` (valid, data, startofpacket, endofpacket).
* Output side: `src_*` (valid, data, channel, startofpacket, endofpac... | controller_mm_interconnect_0_router_005 | uut |
Read the SystemVerilog module `red_pitaya_adv_trigger` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module red_pitaya_adv_trigger #(
parameter COUNTERSZ = 64
)
(
input dac_clk_i,
input reset_i,
input trig_i,
... |
<think>
* DUT: `red_pitaya_adv_trigger`
* Parameters: `COUNTERSZ = 64`
* Inputs: `dac_clk_i`, `reset_i`, `trig_i`, `rearm_i`, `invert_i`, `hysteresis_i`
* Outputs: `trig_o`
* Logic Summary:
* Reset: `triggered=0`, `armed=1`, `counter=hysteresis_i`. `trig_o = 0`.
* Arming: ... | red_pitaya_adv_trigger | red_pitaya_adv_trigger_test |
Read the SystemVerilog module `NOR3X1` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module NOR3X1 (
A,
B,
C,
Y);
input A;
input B;
input C;
output Y;
wire AB_nor;
wire AB_nor_C_nor;
nor(AB_nor, A, B);
nor(AB_nor_C_nor, AB... |
<think>
* DUT: `NOR3X1`
* Logic: `Y = NOR(NOR(A, B), C)` which simplifies to `Y = (A | B) & (~C)`.
* Inputs: `A`, `B`, `C` (1-bit).
* Output: `Y` (1-bit).
* Verification Goal: Exhaustive testing (8 combinations).
* Constraints: Use SystemVerilog, compatible with `iverilog -g2012` (avoid... | NOR3X1 | test_NOR3X1 |
Read the SystemVerilog module `my_dff_reset` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module my_dff_reset (
output reg Q,
input CLK,
input D,
input RESET_B,
input VPWR,
input VGND,
input VPB,
input VNB
);
always @(posed... |
<think>
* DUT: `my_dff_reset` (DFF with asynchronous active-low reset).
* Inputs: `CLK`, `D`, `RESET_B`, `VPWR`, `VGND`, `VPB`, `VNB`.
* Output: `Q`.
* Test Plan requirements:
* Reset Verification (Power-on, Asynchronous trigger, Reset dominance, Reset deassertion).
* Functional... | my_dff_reset | test_my_dff_reset |
Read the SystemVerilog module `accelerator_design` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
////////////////////////////////////////////////////////////////////////////////
// __ _ _ _ //
//... |
<think>
* DUT: `accelerator_design` (8-bit adder, registered output, async reset).
* Inputs: `clk`, `rst`, `in1[7:0]`, `in2[7:0]`.
* Output: `out[8:0]`.
* Behavior: `out <= in1 + in2` on `posedge clk`. `out <= 0` on `posedge rst`.
* Constraint: Must be compatible with `iverilog -g2012` (no cl... | accelerator_design | tb_accelerator_design |
Read the SystemVerilog module `pd_block_mm_interconnect_1_rsp_mux` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
//... |
<think>
* Module Name: `pd_block_mm_interconnect_1_rsp_mux`
* Functionality: It's a multiplexer, but looking at the code, it only has *one* input (`sink0`).
* Logic:
* `src_valid = sink0_valid`
* `src_data = sink0_data`
* `src_channel = sink0_channel`
* `src_starto... | pd_block_mm_interconnect_1_rsp_mux | uut |
Read the SystemVerilog module `top` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
(* top = 1 *)
(* src = "/root/synlig/synlig/tests/simple_tests/ImportParametrizedTypeAndDeclareParamWithTheSameName/top.sv:6.1-10.10" *)
module top(o);
(* src = "... |
<think>
* Module Name: `top`
* Inputs: None.
* Outputs: `o` (32-bit wire).
* Logic: `assign o = 32'd1;`
* Summary: A trivial constant-output module.
* Functional Intent: The module outputs a constant value of 1 (32-bit) on port `o`.
* Interface: Only one output port `o` [31:0].
... | top | test_top |
Read the SystemVerilog module `top_module` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
module transition_detector (
input clk,
input reset,
input [31:0] in,
output reg [31:0] out
);
reg [31:0] in_reg1, in_reg2, in_reg3, in_reg4;
... |
<think>
* DUT: `top_module` containing `transition_detector`.
* Inputs: `clk`, `reset` (async high), `in [31:0]`.
* Outputs: `out [31:0]`.
* Internal signals:
* `in_reg1` to `in_reg4`: A shift register chain of `in`.
* T0: `in`
* T1: `in_reg1` = `in(T-1)`
... | top_module | top_module_verif_tb |
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