prompt stringlengths 450 62.1k | response stringlengths 1.28k 36.6k | top_module stringlengths 1 104 | instance stringlengths 2 109 |
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Read the SystemVerilog module `Regfile` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module Regfile (in1, clk, out,rst);
parameter NUM_WIDTH_LENGTH=13;
input wire [NUM_WIDTH_LENGTH-1:0] in1;
input wire clk;
input logic rst;
output reg [NUM_WIDTH_LENG... |
<think>
* Module: `Regfile`
* Parameter: `NUM_WIDTH_LENGTH = 13`
* Inputs: `in1 [12:0]`, `clk`, `rst`
* Output: `out [13-1:0]`
* Logic: Falling-edge triggered. If `rst == 0`, `out <= in1`. If `rst == 1`, `out <= 0`.
* Observation: The reset is synchronous to the falling edge.
* *... | Regfile | Regfile_verif_tb |
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